Resource-Efficient Model Predictive Control on a Low-End Field-Programmable Gate Array for DC Motor Speed Control

MPC offers advantages in controlling dynamic systems by predicting future behavior based on mathematical models while respecting system constraints. However, increasing model complexity raises the computational burden, which becomes a challenge for low-end FPGAs with limited resources and studies on efficient MPC realization for such platforms remain limited. This study addresses that gap by demonstrating a simplified MPC implementation that maintains real-time performance and acceptable control accuracy while operating within the tight resource constraints of a low-end FPGA (Lattice iCE40HX1K). Several optimization strategies are applied, including simplifying the MPC structure using a 16-bit fixed-point representation (Q13.3), performing model coefficient precomputation outside the FPGA, replacing division operations with equivalent multiplications, minimizing the prediction horizon (), and employing fixed scalar penalty weights to avoid matrix operations. A fully pipelined architecture is designed to ensure deterministic execution timing. A DC motor speed control system is used as a proof-of-concept and tested under false-edge disturbances (2 kHz, 5 kHz, and 10 kHz). Results show that the design operates within the tight logic and memory constraints of the Lattice iCE40HX1K FPGA, utilizing 99% of available logic cells. The proposed design also meets real-time requirements with a computation time of 1.83 µs and maintains consistently stable control performance with steady-state accuracy above 98%. Nevertheless, limited fixed-point precision, a short prediction horizon, and a simplified EMI noise model may reduce robustness under complex disturbances. Overall, the research contribution is the development of a resource-efficient MPC tailored for low-end FPGAs, broadening MPC accessibility beyond mid- to high-end platforms.