Improved Sampling in Carrier-Based Discountinuous SVPWM Simulation

In this study, a circuit was designed to improve sampling in discontinuous SVPWM simulations using Quartus II software. The v_beta_sin unit was successfully simulated using the waveform editor. The results displayed are in accordance with previous calculations, if the input is 000000001 then the output is 100000011 and so on. The v_alfa_cos unit is also successfully simulated using the waveform editor. The simulation results if the input is 000000001 then the output is 111111111 and so on, according to the previous calculation. The unit counter was successfully simulated using the block diagram in Quartus II. The output of this unit counter is in the form of 9 bits to retrieve v_beta_sin and v_alfa_cos data. The v_beta_sin, v_alfa_cos and counter units used as reference signals are successfully simulated and can be used as a supporting circuit in the simulation of the discontinuous SVPWM method. The results of the simulation show an increase in sampling or sampling by 512.